1. Technical Field
The present disclosure relates to structures for communicating electrical signals, and more particularly to through silicon via (TSV) structures.
2. Description of the Related Art
There is an ongoing trend to increase the performance of a semiconductor chip by shifting from a two-dimensional (2D) chip architecture to a three-dimensional (3D) chip architecture. This requires a vertical interconnect between wafer-to-wafer. Through-silicon vias (TSV's), which convey current through stacked Si substrates or Si interposers, represent one component for the creation of three-dimensional integrated circuitry. During the manufacture of TSV's, voids within the conducting material or delamination between the conductor and surrounding environment can lead to failure of the TSV if the current density is sufficiently high. Current methods to detect voids within TSV's involve destructive methods, such as cross-sectional scanning electron microscopy, rendering the part useless.